23 search results - page 3 / 5 » A Unified Compressed Memory Hierarchy |
HIPEAC
2011
Springer
12 years 7 months ago
2011
Springer
For each computer system generation, there are always applications or workloads for which the main memory size is the major limitation. On the other hand, in many cases, one could...
ICPP
2003
IEEE
14 years 19 days ago
2003
IEEE
Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buff...
PPOPP
2012
ACM
12 years 2 months ago
2012
ACM
This paper introduces a programming interface called PARRAY (or Parallelizing ARRAYs) that supports system-level succinct programming for heterogeneous parallel systems like GPU c...
PE
2010
Springer
13 years 2 months ago
2010
Springer
Accurately characterizing the resource usage of an application at various levels in the memory hierarchy has been a long-standing research problem. Existing characterization studi...
ISCAPDCS
2004
13 years 8 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...