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» A VLIW Architecture for Logarithmic Arithmetic
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DSD
2003
IEEE
69views Hardware» more  DSD 2003»
14 years 4 months ago
A VLIW Architecture for Logarithmic Arithmetic
The Logarithmic Number System (LNS) is an alternative to IEEE-754 standard floating-point arithmetic. LNS multiply, divide and square root are easier than IEEE-754 and naturally ...
Mark G. Arnold
TC
2008
13 years 10 months ago
Power and Area-Efficient Unified Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems
A unified computation method of vector and elementary functions is proposed for handheld 3D graphics systems. It unifies vector operations like vector multiply, multiply-and-add, d...
Byeong-Gyu Nam, Hyejung Kim, Hoi-Jun Yoo
DAC
2011
ACM
12 years 10 months ago
Synchronous sequential computation with molecular reactions
Just as electronic systems implement computation in terms of voltage (energy per unit charge), molecular systems compute in terms of chemical concentrations (molecules per unit vo...
Hua Jiang, Marc D. Riedel, Keshab K. Parhi
ASPLOS
2000
ACM
14 years 3 months ago
Communication Scheduling
The high arithmetic rates of media processing applications require architectures with tens to hundreds of functional units, multiple register files, and explicit interconnect betw...
Peter R. Mattson, William J. Dally, Scott Rixner, ...
ARITH
1999
IEEE
14 years 3 months ago
Montgomery Modular Exponentiation on Reconfigurable Hardware
It is widely recognized that security issues will play a crucial role in the majority of future computer and communication systems. Central tools for achieving system security are...
Thomas Blum