DAC 2011 - PDF Preprint Papers

DAC 2011 Design Automation Conference

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DAC
2011
ACM

284views Computer Architecture» more DAC 2011»

Fault-tolerant 3D clock network

13 years 6 days ago

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Clock tree synthesis is one of the most important and challenging problems in 3D ICs. The clock signals have to be delivered by through-silicon vias (TSVs) to different tiers with...

Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu...

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Id	Views	Title	Status

1	284	Fault-tolerant 3D clock network	claim
2	282	Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect	claim
3	275	EFFEX: an embedded processor for computer vision based feature extraction	claim
4	262	Efficient incremental analysis of on-chip power grid via sparse approximation	claim
5	250	Thermal-aware cell and through-silicon-via co-placement for 3D ICs	claim
6	233	Throughput maximization for periodic real-time systems under the maximal temperature constraint	claim
7	215	DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips	claim
8	214	Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC	claim
9	204	Fast non-monte-carlo transient noise analysis for high-precision analog/RF circuits by stochastic orthogonal polynomials	claim
10	200	Process-level virtualization for runtime adaptation of embedded software	claim
11	198	AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection	claim
12	193	Synchronous sequential computation with molecular reactions	claim
13	192	Understanding the impact of power loss on flash memory	claim
14	187	TPM-SIM: a framework for performance evaluation of trusted platform modules	claim
15	186	Rethinking memory redundancy: optimal bit cell repair for maximum-information storage	claim
16	182	Enabling system-level modeling of variation-induced faults in networks-on-chips	claim
17	179	TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC	claim
18	179	ChronOS Linux: a best-effort real-time multiprocessor Linux kernel	claim
19	176	Image quality aware metrics for performance specification of ADC array in 3D CMOS imagers	claim
20	175	Plugging versus logging: a new approach to write buffer management for solid-state disks	claim
21	172	Single-molecule electronic detection using nanoscale field-effect devices	claim
22	166	Generalized reliability-oriented energy management for real-time embedded applications	claim
23	162	Supervised design space exploration by compositional approximation of Pareto sets	claim
24	159	Extracting behavior and dynamically generated hierarchy from SystemC models	claim
25	159	Modeling adaptive streaming applications with parameterized polyhedral process networks	claim
26	153	Implicit permutation enumeration networks and binary decision diagrams reordering	claim
27	150	Customer-aware task allocation and scheduling for multi-mode MPSoCs	claim
28	150	Enforcing architectural contracts in high-level synthesis	claim
29	149	Litmus tests for comparing memory consistency models: how long do they need to be?	claim
30	147	Non-uniform micro-channel design for stacked 3D-ICs	claim

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