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» A Verification Methodology for Model Fields
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136
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SIGSOFT
2007
ACM
16 years 4 months ago
A behavioural model for product families
In this paper we propose a behavioural model, namely the Extended Modal Labeled Transition Systems, as a basis for the formalization of the different notions of variability usuall...
Alessandro Fantechi, Stefania Gnesi
139
Voted
VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
16 years 3 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng
126
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CCR
2004
62views more  CCR 2004»
15 years 3 months ago
Methodological frameworks for large-scale network analysis and design
This paper emphasizes the need for methodological frameworks for analysis and design of large scale networks which are independent of specific design innovations and their advocac...
Antonis Papachristodoulou, Lun Li, John C. Doyle
144
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CLEIEJ
2002
121views more  CLEIEJ 2002»
15 years 3 months ago
Methodological Approach for Developing a KMS: A Case Study
This article describes the construction of a Knowledge Management System (KMS) by applying fundamental concepts and principles of Software Engineering, such as process, models, me...
Anna Grimán, Teresita Rojas, María A...
160
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DT
2006
180views more  DT 2006»
15 years 3 months ago
A SystemC Refinement Methodology for Embedded Software
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...
Jérôme Chevalier, Maxime de Nanclas, ...