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» A Visual Approach to Validating System Level Designs
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ICSE
2004
IEEE-ACM
14 years 9 months ago
Assume-Guarantee Verification of Source Code with Design-Level Assumptions
Model checking is an automated technique that can be used to determine whether a system satisfies certain required properties. To address the "state explosion" problem a...
Dimitra Giannakopoulou, Corina S. Pasareanu, Jamie...
EMSOFT
2010
Springer
13 years 6 months ago
PinaVM: a systemC front-end based on an executable intermediate representation
SystemC is the de facto standard for modeling embedded systems. It allows system design at various levels of abstractions, provides typical object-orientation features and incorpo...
Kevin Marquet, Matthieu Moy
DATE
2006
IEEE
135views Hardware» more  DATE 2006»
14 years 3 months ago
FPGA architecture characterization for system level performance analysis
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
Douglas Densmore, Adam Donlin, Alberto L. Sangiova...
TC
1998
13 years 8 months ago
Design Verification of the S3.mp Cache-Coherent Shared-Memory System
—This paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable emory MultiProcessor (S3.mp) at three levels of abstracti...
Fong Pong, Michael C. Browne, Gunes Aybay, Andreas...
TCOM
2010
106views more  TCOM 2010»
13 years 7 months ago
On the system level prediction of joint time frequency spreading systems with carrier phase noise
- Phase noise is a topic of theoretical and practical interest in electronic circuits. Although progress has been made in the characterization of its description, there are still c...
Youssef Nasser, Mathieu Des Noes, Laurent Ros, Gen...