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ISSS
1999
IEEE
168views Hardware» more  ISSS 1999»
13 years 12 months ago
Automatic Architectural Synthesis of VLIW and EPIC Processors
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
Shail Aditya, B. Ramakrishna Rau, Vinod Kathail
CCGRID
2004
IEEE
13 years 11 months ago
Routing and resource discovery in Phoenix Grid-enabled message passing library
We describe design and implementation of a "Gridenabled" message passing library, in the context of Phoenix message passing model. It supports (1) message routing betwee...
Kenji Kaneda, Kenjiro Taura, Akinori Yonezawa
EUROPAR
2000
Springer
13 years 11 months ago
Design and Evaluation of a Compiler-Directed Collective I/O Technique
Abstract. Current approaches to parallel I/O demand extensive user effort to obtain acceptable performance. This is in part due to difficulties in understanding the characteristics...
Gokhan Memik, Mahmut T. Kandemir, Alok N. Choudhar...
EUROPAR
2010
Springer
13 years 8 months ago
Optimized Dense Matrix Multiplication on a Many-Core Architecture
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...
Elkin Garcia, Ioannis E. Venetis, Rishi Khan, Guan...
INTERNET
2007
105views more  INTERNET 2007»
13 years 7 months ago
Workflow Planning on a Grid
evel of abstraction, we can represent a workflow as a directed graph with operators (or tasks) at the vertices (see Figure 1). Each operator takes inputs from data sources or from ...
Craig W. Thompson, Wing Ning Li, Zhichun Xiao