Sciweavers

183 search results - page 5 / 37
» A case for multi-level main memory
Sort
View
DATE
2010
IEEE
107views Hardware» more  DATE 2010»
14 years 1 months ago
Worst case delay analysis for memory interference in multicore systems
Abstract—Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access...
Rodolfo Pellizzoni, Andreas Schranzhofer, Jian-Jia...
ICCBR
2010
Springer
14 years 14 days ago
Reducing the Memory Footprint of Temporal Difference Learning over Finitely Many States by Using Case-Based Generalization
In this paper we present an approach for reducing the memory footprint requirement of temporal difference methods in which the set of states is finite. We use case-based generaliza...
Matt Dilts, Héctor Muñoz-Avila
CF
2005
ACM
13 years 10 months ago
A case for a working-set-based memory hierarchy
Modern microprocessor designs continue to obtain impressive performance gains through increasing clock rates and advances in the parallelism obtained via micro-architecture design...
Steve Carr, Soner Önder
CACM
2011
113views more  CACM 2011»
13 years 4 days ago
The case for RAMCloud
Disk-oriented approaches to online storage are becoming increasingly problematic: they do not scale gracefully to meet the needs of large-scale Web applications, and improvements ...
John K. Ousterhout, Parag Agrawal, David Erickson,...
PLDI
2011
ACM
12 years 11 months ago
A case for an SC-preserving compiler
The most intuitive memory consistency model for shared-memory multi-threaded programming is sequential consistency (SC). However, current concurrent programming languages support ...
Daniel Marino, Abhayendra Singh, Todd D. Millstein...