1008 search results - page 47 / 202 » A cis-regulatory logic simulator |
CSL
2008
Springer
13 years 10 months ago
2008
Springer
We investigate decidability, complexity and expressive power issues for (first-order) separation logic with one record field (herein called SL) and its fragments. SL can specify pr...
ACL
2009
13 years 6 months ago
2009
We present a new approach to learning a semantic parser (a system that maps natural language sentences into logical form). Unlike previous methods, it exploits an existing syntact...
GLVLSI
1997
IEEE
14 years 27 days ago
1997
IEEE
In a VHDL-based design flow for applicationspecific integrated circuits, VITAL provides a uniform methodology for developing ASIC libraries for signoff simulation. The VITAL Sta...
WSC
2001
13 years 10 months ago
2001
Emulation is a very powerful tool for testing and debugging control code/logic in an office environment rather than on the plant floor. Through the use of emulation, the actual co...
WSC
2008
13 years 11 months ago
2008
In this paper, an automation concept is proposed to facilitate the simulation model building for port design problem. Currently, this process, which includes drawing the terminal ...