1008 search results - page 8 / 202 » A cis-regulatory logic simulator |
TCAD
2008
13 years 8 months ago
2008
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the spe...
KES
2005
Springer
14 years 2 months ago
2005
Springer
This paper presents a system for recognizing sketched logic circuits in real-time and graphically simulating them afterwords. It has been developed for use in university and school...
ICCD
1993
IEEE
14 years 21 days ago
1993
IEEE
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
QEST
2008
IEEE
14 years 3 months ago
2008
IEEE
We tackle the problem of non robustness of simulation and bisimulation when dealing with probabilistic processes. It is important to ignore tiny deviations in probabilities becaus...
PADS
2005
ACM
14 years 2 months ago
2005
ACM
— In this paper, a new event scheduling mechanism XEQ and a new rollback procedure rb-messages are proposed for use in optimistic logic simulation. We incorporate both of these t...