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» A comparative study of power efficient SRAM designs
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ASPDAC
2009
ACM
145views Hardware» more  ASPDAC 2009»
14 years 2 months ago
High performance on-chip differential signaling using passive compensation for global communication
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines is pr...
Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori ...
CEC
2007
IEEE
14 years 2 months ago
Evolvability and Redundancy in Shared Grammar Evolution
— Shared grammar evolution (SGE) is a novel scheme for representing and evolving a population of variablelength programs as a shared set of grammatical productions. Productions t...
Martin H. Luerssen, David M. W. Powers
RTSS
2006
IEEE
14 years 1 months ago
Delay Analysis in Temperature-Constrained Hard Real-Time Systems with General Task Arrivals
In this paper, we study temperature-constrained hard realtime systems, where real-time guarantees must be met without exceeding safe temperature levels within the processor. Dynam...
Shengquan Wang, Riccardo Bettati
GRAPHITE
2005
ACM
14 years 1 months ago
A VR platform for field-scale phenomena: an application to fire spread experiments
Digital computers are powerful tools for studying natural phenomena at large-scales. Nevertheless, custom-made methods have to be developed to digitalize, simulate and finally vis...
Alexandre Muzy, Nicolas Fauvet, Patrick Bourdot, F...
ARCS
2006
Springer
13 years 11 months ago
Dynamic Dictionary-Based Data Compression for Level-1 Caches
Abstract. Data cache compression is actively studied as a venue to make better use of onchip transistors, increase apparent capacity of caches, and hide the long memory latencies. ...
Georgios Keramidas, Konstantinos Aisopos, Stefanos...