802 search results - page 23 / 161 » A comparative study of power efficient SRAM designs |
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
—This paper describes a new low-power, area and pin efficient alternative to differential encoding for high performance chip-to-chip and backplane signaling. The technique, calle...
CASES
2003
ACM
14 years 28 days ago
2003
ACM
Reducing the power consumption of computing devices has gained a lot of attention recently. Many research works have focused on reducing power consumption in the off-chip buses as...
CHI
2000
ACM
14 years 1 days ago
2000
ACM
We have designed and implemented new Web browsing facilities to support effective navigation on Personal Digital Assistants (PDAs) with limited capabilities: low bandwidth, small ...
GLOBECOM
2010
IEEE
13 years 5 months ago
2010
IEEE
In this paper we formulate a power loading problem for the spatial subchannels (parallel channels) of a single-carrier MIMO-SVD system. The power loading solution is designed to mi...
CASES
2006
ACM
13 years 11 months ago
2006
ACM
Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alterna...