Sciweavers

802 search results - page 30 / 161
» A comparative study of power efficient SRAM designs
Sort
View
HIPEAC
2009
Springer
14 years 2 months ago
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that tur...
Michael B. Henry, Leyla Nazhandali
SBCCI
2003
ACM
160views VLSI» more  SBCCI 2003»
14 years 28 days ago
Novel Design Methodology for High-Performance XOR-XNOR Circuit Design
As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequen...
Sumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi
EJWCN
2010
97views more  EJWCN 2010»
13 years 2 months ago
Pricing in Noncooperative Interference Channels for Improved Energy Efficiency
Abstract--We consider noncooperative energy-efficient resource allocation in the interference channel. Energy-efficiency is achieved when each system pays a price proportional to i...
Zhijiat Chong, Rami Mochaourab, Eduard A. Jorswiec...
IDEAL
2003
Springer
14 years 27 days ago
Improving the Efficiency of Frequent Pattern Mining by Compact Data Structure Design
Mining frequent patterns has been a topic of active research because it is computationally the most expensive step in association rule discovery. In this paper, we discuss the use ...
Raj P. Gopalan, Yudho Giri Sucahyo
ISCAS
2007
IEEE
136views Hardware» more  ISCAS 2007»
14 years 2 months ago
Flexible Low Power Probability Density Estimation Unit For Speech Recognition
— This paper describes the hardware architecture for a flexible probability density estimation unit to be used in a Large Vocabulary Speech Recognition System, and targeted for m...
Ullas Pazhayaveetil, Dhruba Chandra, Paul Franzon