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ICPP
1996
IEEE
13 years 11 months ago
Mechanisms for Mapping High-Level Parallel Performance Data
A primary problem in the performance measurement of high-level parallel programming languages is to map lowlevel events to high-level programming constructs. We discuss several as...
R. Bruce Irvin, Barton P. Miller
FPL
2009
Springer
101views Hardware» more  FPL 2009»
14 years 5 days ago
An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure
The creation and optimization of FPGA accelerators comprising several compute cores and memories are challenging tasks in high performance reconfigurable computing. In this paper...
Tobias Schumacher, Christian Plessl, Marco Platzne...
ERSA
2007
86views Hardware» more  ERSA 2007»
13 years 9 months ago
High-Precision BLAS on FPGA-enhanced Computers
The emergence of high-density reconfigurable hardware devices gives scientists and engineers an option to accelerating their numerical computing applications on low-cost but power...
Chuan He, Guan Qin, Richard E. Ewing, Wei Zhao
WWW
2009
ACM
14 years 8 months ago
Using graphics processors for high performance IR query processing
Web search engines are facing formidable performance challenges as they need to process thousands of queries per second over billions of documents. To deal with this heavy workloa...
Shuai Ding, Jinru He, Hao Yan, Torsten Suel
ASPLOS
2010
ACM
14 years 2 months ago
MacroSS: macro-SIMDization of streaming applications
SIMD (Single Instruction, Multiple Data) engines are an essential part of the processors in various computing markets, from servers to the embedded domain. Although SIMD-enabled a...
Amir Hormati, Yoonseo Choi, Mark Woh, Manjunath Ku...