ASPLOS 2010 - PDF Preprint Papers

ASPLOS 2010 Architectural Support for Programming Languages and Operating Systems

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ASPLOS
2010
ACM

701views Programming Languages» more ASPLOS 2010»

The Scalable Heterogeneous Computing (SHOC) benchmark suite

14 years 7 months ago

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Scalable heterogeneous computing systems, which are composed of a mix of compute devices, such as commodity multicore processors, graphics processors, reconﬁgurable processors, ...

Anthony Danalis, Gabriel Marin, Collin McCurdy, Je...

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Id	Views	Title	Status

1	701	The Scalable Heterogeneous Computing (SHOC) benchmark suite	claim
2	359	SherLog: error diagnosis by connecting clues from run-time logs	claim
3	359	Accelerating SQL database operations on a GPU with CUDA	claim
4	328	Dynamically replicated memory: building reliable systems from nanoscale resistive memories	claim
5	325	Accelerating the local outlier factor algorithm on a GPU for intrusion detection systems	claim
6	294	Conservation cores: reducing the energy of mature computations	claim
7	287	Butterfly analysis: adapting dataflow analysis to dynamic parallel monitoring	claim
8	286	Cortical architectures on a GPGPU	claim
9	278	Decoupling contention management from scheduling	claim
10	277	Addressing shared resource contention in multicore processors via scheduling	claim
11	268	A randomized scheduler with probabilistic guarantees of finding bugs	claim
12	268	An asymmetric distributed shared memory model for heterogeneous parallel systems	claim
13	265	Speculative parallelization using software multi-threaded transactions	claim
14	265	Accelerating MATLAB Image Processing Toolbox functions on GPUs	claim
15	262	CoreDet: a compiler and runtime system for deterministic multithreaded execution	claim
16	256	Request behavior variations	claim
17	250	A real system evaluation of hardware atomicity for software speculation	claim
18	247	MacroSS: macro-SIMDization of streaming applications	claim
19	245	Virtualized and flexible ECC for main memory	claim
20	241	Analyzing multicore dumps to facilitate concurrency bug reproduction	claim
21	240	Power routing: dynamic power provisioning in the data center	claim
22	230	COMPASS: a programmable data prefetcher using idle GPU shaders	claim
23	229	Characterizing processor thermal behavior	claim
24	228	Micro-pages: increasing DRAM efficiency with locality-aware data placement	claim
25	222	Flexible architectural support for fine-grain scheduling	claim
26	217	ConMem: detecting severe concurrency bugs through an effect-oriented approach	claim
27	217	Modeling GPU-CPU workloads and systems	claim
28	217	Orthrus: efficient software integrity protection on multi-cores	claim
29	216	Best-effort semantic document search on GPUs	claim
30	212	Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems	claim
31	207	Implementing the PGI Accelerator model	claim
32	205	Specifying and dynamically verifying address translation-aware memory consistency	claim
33	205	Dynamic filtering: multi-purpose architecture support for language runtime systems	claim
34	203	A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing	claim
35	202	Probabilistic job symbiosis modeling for SMT processor scheduling	claim
36	191	Shoestring: probabilistic soft error reliability on the cheap	claim
37	186	ParaLog: enabling and accelerating online parallel monitoring of multithreaded applications	claim

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