Sciweavers

468 search results - page 32 / 94
» A compiler for high performance computing with many-core acc...
Sort
View
ISCAS
2006
IEEE
101views Hardware» more  ISCAS 2006»
15 years 11 months ago
A cost-effective reconfigurable accelerator for platform-based SOC design
In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-on-a-chip (SoC) design. Based on the proposed design methodology, the reconfigu...
Lan-Da Van, Hsin-Fu Luo, Nien-Hsiang Chang, Chun-M...
FCCM
1998
IEEE
119views VLSI» more  FCCM 1998»
15 years 9 months ago
Specifying and Compiling Applications for RaPiD
E cient, deeply pipelined implementations exist for a wide variety of important computation-intensive applications, and many special-purpose hardware machines have been built that...
Darren C. Cronquist, Paul Franklin, Stefan G. Berg...
136
Voted
PLDI
2010
ACM
15 years 10 months ago
A GPGPU compiler for memory optimization and parallelism management
This paper presents a novel optimizing compiler for general purpose computation on graphics processing units (GPGPU). It addresses two major challenges of developing high performa...
Yi Yang, Ping Xiang, Jingfei Kong, Huiyang Zhou
149
Voted
SIGGRAPH
1999
ACM
15 years 9 months ago
Realistic, Hardware-Accelerated Shading and Lighting
With fast 3D graphics becoming more and more available even on low end platforms, the focus in hardware-accelerated rendering is beginning to shift towards higher quality renderin...
Wolfgang Heidrich, Hans-Peter Seidel
CGF
2011
14 years 8 months ago
Two-Level Grids for Ray Tracing on GPUs
We investigate the use of two-level nested grids as acceleration structure for ray tracing of dynamic scenes. We propose a massively parallel, sort-based construction algorithm an...
Javor Kalojanov, Markus Billeter, Philipp Slusalle...