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IEEEPACT
2000
IEEE
14 years 4 hour ago
Global Register Partitioning
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
Jason Hiser, Steve Carr, Philip H. Sweany
HIPC
1999
Springer
13 years 12 months ago
Microcaches
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
David May, Dan Page, James Irwin, Henk L. Muller
FCCM
2011
IEEE
251views VLSI» more  FCCM 2011»
12 years 11 months ago
A Scalable Multi-FPGA Platform for Complex Networking Applications
Abstract—Ballooning traffic volumes and increasing linkspeeds require ever high compute power to perform complex real-time processing of network packets. FPGAs have already been...
Sascha Mühlbach, Andreas Koch
DAC
2007
ACM
14 years 8 months ago
Chip Multi-Processor Generator
The drive for low-power, high performance computation coupled with the extremely high design costs for ASIC designs, has driven a number of designers to try to create a flexible, ...
Alex Solomatnikov, Amin Firoozshahian, Wajahat Qad...
ARC
2010
Springer
387views Hardware» more  ARC 2010»
14 years 2 months ago
Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods
Computing the solution to a system of linear equations is a fundamental problem in scientific computing, and its acceleration has drawn wide interest in the FPGA community [1–3]...
David Boland, George A. Constantinides