Sciweavers

672 search results - page 7 / 135
» A compiler-based communication analysis approach for multipr...
Sort
View
CJ
2006
84views more  CJ 2006»
13 years 7 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
IPPS
2008
IEEE
14 years 1 months ago
Symbolic expression analysis for compiled communication
Enabling circuit switching in multiprocessor systems has the potential to achieve more efficient communication with lower cost compared to packet/wormhole switching. However, in ...
Shuyi Shao, Yu Zhang, Alex K. Jones, Rami G. Melhe...
ASAP
2000
IEEE
142views Hardware» more  ASAP 2000»
13 years 12 months ago
Contention-Conscious Transaction Ordering in Embedded Multiprocessors
This paper explores the problem of efficiently ordering interprocessor communication operations in statically-scheduled multiprocessors for iterative dataflow graphs. In most digi...
Mukul Khandelia, Shuvra S. Bhattacharyya
ERSA
2007
177views Hardware» more  ERSA 2007»
13 years 9 months ago
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...
Xiaofang Wang, Sotirios G. Ziavras, Jie Hu
CODES
2006
IEEE
14 years 1 months ago
Bounded arbitration algorithm for QoS-supported on-chip communication
Time-critical multi-processor systems require guaranteed services in terms of throughput, bandwidth etc. in order to comply to hard real-time constraints. However, guaranteedservi...
Mohammad Abdullah Al Faruque, Gereon Weiss, Jö...