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» A computational architecture for heterogeneous reasoning
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ICS
2003
Tsinghua U.
14 years 2 months ago
AEGIS: architecture for tamper-evident and tamper-resistant processing
We describe the architecture for a single-chip aegis processor which can be used to build computing systems secure against both physical and software attacks. Our architecture ass...
G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, M...
ICPP
2009
IEEE
14 years 3 months ago
Speeding Up Distributed MapReduce Applications Using Hardware Accelerators
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
Yolanda Becerra, Vicenç Beltran, David Carr...
CORR
2010
Springer
157views Education» more  CORR 2010»
13 years 9 months ago
Context Ontology Implementation for Smart Home
Context awareness is one of the important fields in ubiquitous computing. Smart Home, a specific instance of ubiquitous computing, provides every family with opportunities to enjo...
Tam Van Nguyen, Wontaek Lim, Huy Anh Nguyen, Deokj...
ICSOC
2007
Springer
14 years 3 months ago
Let It Flow: Building Mashups with Data Processing Pipelines
Mashups are a new kind of interactive Web application, built out of the composition of two or more existing Web service APIs and data sources. Whereas “pure” mashups are built ...
Biörn Biörnstad, Cesare Pautasso
CODES
2005
IEEE
14 years 2 months ago
Retargetable generation of TLM bus interfaces for MP-SoC platforms
In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cor...
Andreas Wieferink, Rainer Leupers, Gerd Ascheid, H...