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» A data architecture for consumer RFID applications
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ISQED
2008
IEEE
154views Hardware» more  ISQED 2008»
14 years 1 months ago
Error Protected Data Bus Inversion Using Standard DRAM Components
Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialized memories or assume error free environments. This i...
Maurizio Skerlj, Paolo Ienne
DAC
2007
ACM
14 years 8 months ago
Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification
Programming multi-processor systems-on-chip (MPSoC) involves partitioning and mapping of sequential reference code onto multiple parallel processing elements. The immense potentia...
Pramod Chandraiah, Rainer Dömer
ANCS
2009
ACM
13 years 5 months ago
Design and performance analysis of a DRAM-based statistics counter array architecture
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim...
SAC
2011
ACM
12 years 10 months ago
Cloud application logging for forensics
Logs are one of the most important pieces of analytical data in a cloud-based service infrastructure. At any point in time, service owners and operators need to understand the sta...
Raffael Marty
ASPDAC
2005
ACM
111views Hardware» more  ASPDAC 2005»
13 years 9 months ago
Wave-pipelined on-chip global interconnect
— A novel wave-pipelined global interconnect system is developed for reliable, high throughput, on-chip data communication. We argue that because there is only a single signal pr...
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen