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93
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IPPS
1998
IEEE
15 years 7 months ago
A Scalable VLSI Architecture for Binary Prefix Sums
The task of computingbinary prefix sums (BPS, for short) arises, for example, in expression evaluation, data and storage compaction, and routing. This paper describes a scalable V...
Rong Lin, Koji Nakano, Stephan Olariu, Maria Crist...
138
Voted
CCGRID
2007
IEEE
15 years 10 months ago
A Hierarchical Two-Tier Information Management Architecture for Mobile Ad-Hoc Grid Environments
A novel management layer architecture for mobile grid environments and ad-hoc networks is presented. This paper addresses a key challenge in dynamic mobile environments with a hig...
Joachim Zottl, Wilfried N. Gansterer, Helmut Hlava...
120
Voted
IPPS
2007
IEEE
15 years 9 months ago
Rethinking Automated Synthesis of MPSoC Architectures
Emerging heterogeneous multiprocessors will have custom memory and bus architectures that must balance resource sharing and system partitioning to meet cost constraints. We propos...
Brett H. Meyer, Donald E. Thomas
132
Voted
ICPP
1995
IEEE
15 years 7 months ago
The Application of Skewed-Associative Memories to Cache Only Memory Architectures
— Skewed-associative caches use several hash functions to reduce collisions in caches without increasing the associativity. This technique can increase the hit ratio of a cache w...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
148
Voted
IPPS
2010
IEEE
15 years 1 months ago
Restructuring parallel loops to curb false sharing on multicore architectures
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
Santosh Sarangkar, Apan Qasem