Restructuring parallel loops to curb false sharing on multicore architectures

The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities for performance gains for multi-threaded applications. However, when not handled carefully, contention for the shared-cache can lead to performance degradation. This paper addresses the issue of cache interference that occurs when concurrent threads access data that reside on a shared cache block. We propose a new compiler technique that takes advantage of hardware prefetching and thread affinity features to ameliorate performance loss due to this type of interference. Preliminary evaluation on a dual-core and a quad-core platform shows that our strategy can be effective in reducing cache interference for multi-threaded applications that exhibit inter-core spatial locality. Keywords-shared-cache; memory hierarchy; multicore; performance

• Type: Journal
• Year: 2010
• Where: IPPS
• Authors: Santosh Sarangkar, Apan Qasem
• Keywords: Cache, Distributed And Parallel Computing, IPPS 2010, Memory Hierarchy, Multi-threaded Applications