197 search results - page 30 / 40 » A design workflow for dynamically reconfigurable multi-FPGA ... |
DAC
2007
ACM
14 years 7 months ago
2007
ACM
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
CDC
2008
IEEE
13 years 6 months ago
2008
IEEE
This paper is a response to requests from several respected colleagues in academia for a careful writeup of the classical time-optimal control based hybrid controllers that we have...
LCPC
2000
Springer
13 years 10 months ago
2000
Springer
State-of-the-art run-time systems are a poor match to diverse, dynamic distributed applications because they are designed to provide support to a wide variety of applications, with...
DATE
2009
IEEE
14 years 1 months ago
2009
IEEE
—Partial Reconfiguration (PR) of FPGAs presents many opportunities for application design flexibility, enabling tasks to dynamically swap in and out of the FPGA without entire sy...
MAM
2007
13 years 6 months ago
2007
This paper describes a new method of executing a software program on an FPGA for embedded systems. Rather than combine reconfigurable logic with a microprocessor core, this method...