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» A digit serial algorithm for the integer power operation
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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 4 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
PIMRC
2010
IEEE
13 years 5 months ago
A green software-defined communication processor for dynamic spectrum access
Abstract--Dynamic spectrum access (DSA) supporting opportunistic transmission without extra spectrum bandwidth is attractive for future wireless communication. To facilitate such D...
Ching-Kai Liang, Kwang-Cheng Chen
GECCO
2008
Springer
144views Optimization» more  GECCO 2008»
13 years 8 months ago
Multi-resistant radar jamming using genetic algorithms
The next generation of advanced self-protection jammers is expected to deliver effective and energy efficient jamming against modern air tracking radars. However, optimizing such ...
Hans Jonas Fossum Moen, Stein Kristoffersen
EMSOFT
2010
Springer
13 years 5 months ago
Power-aware temporal isolation with variable-bandwidth servers
Variable-bandwidth servers (VBS) control process execution speed by allocating variable CPU bandwidth to processes. VBS enables temporal isolation of EDF-scheduled processes in th...
Silviu S. Craciunas, Christoph M. Kirsch, Ana Soko...
ISCAS
2006
IEEE
145views Hardware» more  ISCAS 2006»
14 years 1 months ago
The wordlength determination problem of linear time invariant systems with multiple outputs - a geometric programming approach
This paper proposes two new methods for optimizing objectives and constraints. The GP approach is very general and hardware resources in finite wordlength implementation of it allo...
S. C. Chan, K. M. Tsui