Sciweavers

182 search results - page 6 / 37
» A distributed processor state management architecture for la...
Sort
View
CF
2009
ACM
14 years 2 months ago
Strategies for dynamic memory allocation in hybrid architectures
Hybrid architectures combining the strengths of generalpurpose processors with application-specific hardware accelerators can lead to a significant performance improvement. Our ...
Peter Bertels, Wim Heirman, Dirk Stroobandt
IPPS
2006
IEEE
14 years 1 months ago
Dynamic configuration steering for a reconfigurable superscalar processor
A new dynamic vector approach for the selection and management of the configuration of a reconfigurable superscalar processor is proposed. This new method improves on previous wor...
Nick A. Mould, Brian F. Veale, Monte P. Tull, John...
DAC
2000
ACM
14 years 8 months ago
Synthesis and optimization of coordination controllers for distributed embedded systems
A main advantage of control composition with modal processes [4] is the enhanced retargetability of the composed behavior over a wide variety of target architectures. Unlike previ...
Pai H. Chou, Gaetano Borriello
HPCA
2003
IEEE
14 years 8 months ago
Mini-Threads: Increasing TLP on Small-Scale SMT Processors
Several manufacturers have recently announced the first simultaneous-multithreaded processors, both as single CPUs and as components of multi-CPU chips. All are small scale, compr...
Joshua Redstone, Susan J. Eggers, Henry M. Levy
ICCD
2004
IEEE
101views Hardware» more  ICCD 2004»
14 years 4 months ago
Increasing Processor Performance Through Early Register Release
Modern superscalar microprocessors need sizable register files to support large number of in-flight instructions for exploiting ILP. An alternative to building large register file...
Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kan...