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IEEEPACT
2009
IEEE
14 years 2 months ago
StealthTest: Low Overhead Online Software Testing Using Transactional Memory
—Software testing is hard. The emergence of multicore architectures and the proliferation of bugprone multithreaded software makes testing even harder. To this end, researchers h...
Jayaram Bobba, Weiwei Xiong, Luke Yen, Mark D. Hil...
WSC
1998
13 years 8 months ago
Communication Mission-type Orders to Virtual Commanders
This paper discusses issues in modeling C4I and cognitive processes in next generation simulations and applications to Force XXI command and control. We propose a modification to ...
Martin S. Kleiner, Scott A. Carey, Joseph E. Beach
ISCA
2009
IEEE
152views Hardware» more  ISCA 2009»
14 years 2 months ago
Scaling the bandwidth wall: challenges in and avenues for CMP scaling
As transistor density continues to grow at an exponential rate in accordance to Moore’s law, the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-ch...
Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken...
PVM
2009
Springer
14 years 2 months ago
MPI on a Million Processors
Petascale machines with close to a million processors will soon be available. Although MPI is the dominant programming model today, some researchers and users wonder (and perhaps e...
Pavan Balaji, Darius Buntinas, David Goodell, Will...
ISCA
1997
IEEE
96views Hardware» more  ISCA 1997»
13 years 11 months ago
DataScalar Architectures
DataScalar architectures improve memory system performance by running computation redundantly across multiple processors, which are each tightly coupled with an associated memory....
Doug Burger, Stefanos Kaxiras, James R. Goodman