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» A fast algorithm for power grid design
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GLVLSI
2003
IEEE
129views VLSI» more  GLVLSI 2003»
14 years 27 days ago
A system-level methodology for fast multi-objective design space exploration
In this paper, we address the problem of the efficient exploration of the architectural design space for parameterized systems. Since the design space is multi-objective, our aim ...
Gianluca Palermo, Cristina Silvano, S. Valsecchi, ...
BMCBI
2010
84views more  BMCBI 2010»
13 years 7 months ago
A variational Bayes algorithm for fast and accurate multiple locus genome-wide association analysis
Background: The success achieved by genome-wide association (GWA) studies in the identification of candidate loci for complex diseases has been accompanied by an inability to expl...
Benjamin A. Logsdon, Gabriel E. Hoffman, Jason G. ...
DAC
2004
ACM
14 years 8 months ago
Efficient power/ground network analysis for power integrity-driven design methodology
As technology advances, the metal width is decreasing with the length increasing, making the resistance along the power line increase substantially. Together with the nonlinear sc...
Su-Wei Wu, Yao-Wen Chang
PEWASUN
2004
ACM
14 years 1 months ago
A routing protocol for power constrained networks with asymmetric links
In many instances, an ad hoc network consists of nodes with different hardware and software capabilities as well as power limitations. This is the case of ad hoc grids where devi...
Guoqiang Wang, Yongchang Ji, Dan C. Marinescu, Dam...
VLSID
2005
IEEE
100views VLSI» more  VLSID 2005»
14 years 8 months ago
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model
Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay ...
Yibo Wang, Yici Cai, Xianlong Hong