Sciweavers

195 search results - page 30 / 39
» A fast algorithm for power grid design
Sort
View
TON
2008
124views more  TON 2008»
13 years 7 months ago
Designing packet buffers for router linecards
-- Internet routers and Ethernet switches contain packet buffers to hold packets during times of congestion. Packet buffers are at the heart of every packet switch and router, whic...
Sundar Iyer, Ramana Rao Kompella, Nick McKeown
VLSID
2002
IEEE
126views VLSI» more  VLSID 2002»
14 years 8 months ago
A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication
With the projected significant growth in mobile internet and multimedia services, there is a strong demand for nextgeneration appliances capable of wireless image communication. O...
Debashis Panigrahi, Clark N. Taylor, Sujit Dey
SIGCOMM
2009
ACM
14 years 2 months ago
PLUG: flexible lookup modules for rapid deployment of new protocols in high-speed routers
New protocols for the data link and network layer are being proposed to address limitations of current protocols in terms of scalability, security, and manageability. High-speed r...
Lorenzo De Carli, Yi Pan, Amit Kumar, Cristian Est...
ACMMSP
2006
ACM
232views Hardware» more  ACMMSP 2006»
14 years 1 months ago
Implicit and explicit optimizations for stencil computations
Stencil-based kernels constitute the core of many scientific applications on block-structured grids. Unfortunately, these codes achieve a low fraction of peak performance, due pr...
Shoaib Kamil, Kaushik Datta, Samuel Williams, Leon...
SLIP
2003
ACM
14 years 24 days ago
Error-correction and crosstalk avoidance in DSM busses
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
Ketan N. Patel, Igor L. Markov