22 search results - page 3 / 5 » A fill-unit approach to multiple instruction issue |
EUROMICRO
1999
IEEE
13 years 11 months ago
1999
IEEE
This paper describes the DELFT-JAVA processor and the mechanisms required to dynamically translate JVM instructions into DELFT-JAVA instructions. Using a form of hardware register...
IEEEPACT
2002
IEEE
14 years 12 days ago
2002
IEEE
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...
MICRO
1995
IEEE
13 years 11 months ago
1995
IEEE
Untolerated load instruction latencies often have a significant impact on overall program performance. As one means of mitigating this effect, we present an aggressive hardware-b...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
IPPS
1998
IEEE
13 years 11 months ago
1998
IEEE
With aggressive superscalar processors delivering diminishing returns, alternate designs that make good use of the increasing chip densities are actively being explored. One such ...