303 search results - page 5 / 61 » A formal executable semantics of Verilog |
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
FMOODS
2006
13 years 9 months ago
2006
In this paper we describe an application of the theory of graph transformations to the practise of language design. In particular, we have defined the static and dynamic semantics ...
ENTCS
2007
13 years 7 months ago
2007
Most large-scaled software systems are structured in distributed components to manage complexity and have to cope with concurrent executed threads. System decomposition and concur...
ICECCS
2007
IEEE
14 years 2 months ago
2007
IEEE
Semantic Web Services, one of the most significant research areas within the Semantic Web vision, has attracted increasing attention from both the research community and industry...
SPIN
2000
Springer
13 years 11 months ago
2000
Springer
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...