496 search results - page 39 / 100 » A formal framework for synthesis and verification of logic p... |
POPL
2004
ACM
14 years 8 months ago
2004
ACM
We prove the decidability of the quantifier-free, static fragment of ambient logic, with composition adjunct and iteration, which corresponds to a kind of regular expression langu...
WFLP
2000
Springer
13 years 11 months ago
2000
Springer
We introduce a framework for assessing the effectiveness of partial evaluators in functional logic languages. Our framework is based on properties of the rewrite system that models...
ICTAC
2005
Springer
14 years 1 months ago
2005
Springer
Rewriting logic is a simple computational logic very well suited as a semantic framework within which many different models of computation, systems and languages can be naturally ...
SIGSOFT
2007
ACM
14 years 8 months ago
2007
ACM
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
PLPV
2011
ACM
12 years 10 months ago
2011
ACM
Soundness proofs of program logics such as Hoare logics and type systems are often made easier by decorating the operational semantics with information that is useful in the proof...