496 search results - page 52 / 100 » A formal framework for synthesis and verification of logic p... |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
- Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-bas...
CHARME
2003
Springer
14 years 26 days ago
2003
Springer
We present a non-operational approach to specifying and analyzing shared memory consistency models. The method uses higher order logic to capture a complete set of ordering constra...
ATVA
2010
Springer
13 years 5 months ago
2010
Springer
Exception handling is an important language feature for building more robust software programs. It is primarily concerned with capturing abnormal events, with the help of catch han...
IBERAMIA
2010
Springer
13 years 5 months ago
2010
Springer
In a recent paper [2] the authors have formalized a recursive semantics for warranted conclusions in a general defeasible argumentation framework based on a propositional logic. Th...
SPIN
2000
Springer
13 years 11 months ago
2000
Springer
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...