As technology scales down, timing verification of digital integrated circuits becomes an increasingly challenging task due to the gate and wire variability. Therefore, statistical...
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that...
In the nanometer manufacturing region, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus dev...
—We present a new technique for statistical static timing analysis (SSTA) based on Markov chain Monte Carlo (MCMC), that allows fast and accurate estimation of the right-hand tai...
Yashodhan Kanoria, Subhasish Mitra, Andrea Montana...
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukher...