246 search results - page 25 / 50 » A functional formalization of on chip communications |
CF
2004
ACM
14 years 6 days ago
2004
ACM
Centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption and are thus not suitable for consumer electronic devices. The conse...
CP
2006
Springer
13 years 10 months ago
2006
Springer
This paper describes a complete and efficient solution to the stochastic allocation and scheduling for Multi-Processor System-on-Chip (MPSoC). Given a conditional task graph charac...
ERSA
2006
13 years 8 months ago
2006
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
ASAP
2007
IEEE
13 years 7 months ago
2007
IEEE
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single system on chip (SoC) currently, and the number is likely to increase significa...
GLOBECOM
2008
IEEE
13 years 7 months ago
2008
IEEE
As the network line rates reach 40 Gbps today and 100 Gbps in the near future, performing deep packet inspection (DPI) in the Network Intrusion Detection and Prevention Systems (NI...