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» A functional formalization of on chip communications
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TCAD
2010
105views more  TCAD 2010»
13 years 1 months ago
Fault Tolerant Network on Chip Switching With Graceful Performance Degradation
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...
Adán Kohler, Gert Schley, Martin Radetzki
FMCAD
2006
Springer
13 years 10 months ago
Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning
Pervasive Logic is a broad term applied to the variety of logic present in hardware designs, yet not a part of their primary functionality. Examples of pervasive logic include init...
Tilman Glökler, Jason Baumgartner, Devi Shanm...
ASAP
1996
IEEE
96views Hardware» more  ASAP 1996»
13 years 11 months ago
Kestrel: A Programmable Array for Sequence Analysis
Kestrel is a programmable linear array processor designed for sequence analysis. Among other features, Kestrel includes an 8-bit word, a single-cycle add-and-minimize instruction, ...
Jeffrey D. Hirschberg, Richard Hughey, Kevin Karpl...
ICIP
1999
IEEE
14 years 8 months ago
Architecture of Embedded Video Processing in a Multimedia Chip-Set
A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-win...
Egbert G. T. Jaspers, Peter H. N. de With
ISCA
2007
IEEE
106views Hardware» more  ISCA 2007»
14 years 1 months ago
Architectural implications of brick and mortar silicon manufacturing
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, ...