3 search results - page 1 / 1 » A general decomposition strategy for verifying register rena... |
DAC
2004
ACM
14 years 12 months ago
2004
ACM
This paper describes a strategy for verifying data-hazard correctness of out-of-order processors that implement register-renaming. We define a set of predicates to characterize re...
GLVLSI
2002
IEEE
14 years 3 months ago
2002
IEEE
As an efficient representation of Extended Finite State Machines, Multiway Decision Graphs (MDG) are suitable for automatic hardware verification of Register Transfer Level (RTL) ...
LCTRTS
2009
Springer
14 years 5 months ago
2009
Springer
Register allocation is often a two-phase approach: spilling of registers to memory, followed by coalescing of registers. Extreme liverange splitting (i.e. live-range splitting aft...