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ASAP
2006
IEEE
111views Hardware» more  ASAP 2006»
14 years 2 months ago
Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions
Current microprocessor instruction set architectures are word oriented, with some subword support. Many important applications, however, can realize substantial performance benefi...
Yedidya Hilewitz, Ruby B. Lee
ISCAS
2006
IEEE
120views Hardware» more  ISCAS 2006»
14 years 2 months ago
Fast bit permutation unit for media enhanced microprocessors
— Bit and subword permutations are useful in many multimedia and cryptographic applications. New shift and permute instructions have been added to the instruction set of general-...
Giorgos Dimitrakopoulos, Christos Mavrokefalidis, ...
ISCAS
2006
IEEE
103views Hardware» more  ISCAS 2006»
14 years 2 months ago
A neural model for sonar-based navigation in obstacle fields
— The rapid control of sonar-guided vehicles through obstacle fields has been a goal of robotics for decades. How sensory data is represented strongly affects how obstacles and g...
Timothy K. Horiuchi
ISCAS
2006
IEEE
74views Hardware» more  ISCAS 2006»
14 years 2 months ago
NIUGAP: low latency network interface architecture with Gray code for networks-on-chip
— The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP c...
Daewook Kim, Manho Kim, Gerald E. Sobelman
CAMP
2005
IEEE
14 years 1 months ago
A Plug-and-Play Architecture for Cognitive Video Stream Analysis
— This paper presents an architecture for cognitive analysis of streaming video, in which a new module can easily be plugged in, to add to or even compete with existing functiona...
Thor List, José Bins, Robert B. Fisher, Dav...