Sciweavers

    1013 search results - page 22 / 203
    » A hardware implementation of realloc function
    Sort
    View
    IJNS
    2000
    80views more  IJNS 2000»
    VLSI Implementation of Neural Networks
    13 years 7 months ago
    VLSI Implementation of Neural Networks
    Download  www.eng.auburn.edu
    Currently, fuzzy controllers are the most popular choice for hardware implementation of complex control surfaces because they are easy to design. Neural controllers are more compl...
    Bogdan M. Wilamowski, J. Binfet, M. O. Kaynak
    claim paper
    Read More »
    ERSA
    2009
    387views Hardware» more  ERSA 2009»
    Implementation of the Gauss-Newton Algorithm for Non-linear Least-mean-squares Fitting in FPGA Devices
    13 years 5 months ago
    Implementation of the Gauss-Newton Algorithm for Non-linear Least-mean-squares Fitting in FPGA Devices
    Download  risorse.dei.polimi.it
    Abstract-- The paper presents the implementation of nonlinear least-squares regression in a Field Programmable Gate Array (FPGA) device. The implemented algorithm is very performan...
    Andrea Abba, Antonio Manenti, Andrea Suardi, Angel...
    claim paper
    Read More »
    ISMVL
    1998
    IEEE
    109views Hardware» more  ISMVL 1998»
    Implementing a Multiple-Valued Decision Diagram Package
    14 years 1 days ago
    Implementing a Multiple-Valued Decision Diagram Package
    Download  webhome.cs.uvic.ca
    Decision diagrams are the state-of-the-art representation for logic functions, both binary and multiple-valued. Here we consider issues regarding the efficient implementation of a...
    D. Miller, Rolf Drechsler
    claim paper
    Read More »
    APCCAS
    2006
    IEEE
    251views Hardware» more  APCCAS 2006»
    Implementation of a H.264 decoder with Template-based Communication Refinement
    14 years 1 months ago
    Implementation of a H.264 decoder with Template-based Communication Refinement
    Download  s-space.snu.ac.kr
    We described an H.264 decoder implemented with our design methodology, in which a system function model of transaction level is first captured in SystemC and refined into RTL with ...
    Sang-yong Yoon, Sanggyu Park, Soolk Chae
    claim paper
    Read More »
    ASPDAC
    2011
    ACM
    215views Hardware» more  ASPDAC 2011»
    An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
    12 years 11 months ago
    An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
    Download  www.kameyama.ecei.tohoku.ac.jp
    —This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small...
    Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama...
    claim paper
    Read More »
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.