Sciweavers

5309 search results - page 1031 / 1062
» A high performance Erlang system
Sort
View
EMSOFT
2005
Springer
14 years 2 months ago
Optimizing inter-processor data locality on embedded chip multiprocessors
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
Guilin Chen, Mahmut T. Kandemir
ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
14 years 1 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...
ICS
2001
Tsinghua U.
14 years 28 days ago
Optimizing strategies for telescoping languages: procedure strength reduction and procedure vectorization
At Rice University, we have undertaken a project to construct a framework for generating high-level problem solving languages that can achieve high performance on a variety of pla...
Arun Chauhan, Ken Kennedy
ANSS
2000
IEEE
14 years 27 days ago
Flow Control and Dynamic Load Balancing in Time Warp
We present, in this paper, an algorithm which integrates flow control and dynamic load balancing in Time Warp. The algorithm is intended for use in a distributed memory environme...
Myongsu Choe, Carl Tropper
ICNP
2000
IEEE
14 years 26 days ago
A Scalable Monitoring Approach for Service Level Agreements Validation
In order to detect violations of end-to-end service level agreements (SLA) and to isolate trouble links and nodes based on a unified framework, managers of a service provider net...
Mun Choon Chan, Yow-Jian Lin, Xin Wang
« Prev « First page 1031 / 1062 Last » Next »