2209 search results - page 232 / 442 » A high performance JPEG2000 architecture |
VLSID
2009
IEEE
14 years 10 months ago
2009
IEEE
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
ICASSP
2008
IEEE
14 years 4 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
IPPS
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper proposes the study of a new computation model that attempts to address the underlying sources of performance degradation (e.g. latency, overhead, and starvation) and th...
ISVLSI
2007
IEEE
14 years 4 months ago
2007
IEEE
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
APCSAC
2005
IEEE
14 years 3 months ago
2005
IEEE
Moore’s law describes the growth in on-chip transistor density, which doubles every 18 to 24 months and looks set to continue for at least a decade and possibly longer. This grow...