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» A high performance JPEG2000 architecture
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ICCD
2004
IEEE
158views Hardware» more  ICCD 2004»
14 years 6 months ago
An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing
A programmable parallel digital signal processor (DSP) core for embedded applications is presented which combines the concepts of single instruction stream over multiple data stre...
Liang Han, Jie Chen, Chaoxian Zhou, Ying Li, Xin Z...
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
14 years 6 months ago
Design and Implementation of Scalable Low-Power Montgomery Multiplier
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
Hee-Kwan Son, Sang-Geun Oh
ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
14 years 6 months ago
Fast and accurate transaction level models using result oriented modeling
Efficient communication modeling is a critical task in SoC design and exploration. In particular, fast and accurate communication is needed to predict the performance of a system....
Gunar Schirner, Rainer Dömer
ICS
2009
Tsinghua U.
14 years 3 months ago
Parametric multi-level tiling of imperfectly nested loops
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
Albert Hartono, Muthu Manikandan Baskaran, C&eacut...
HAPTICS
2009
IEEE
14 years 3 months ago
Perceptual coding of haptic data in time-delayed teleoperation
In telepresence and teleaction systems the haptic communication channel plays a central role. As it closes a global control loop any introduced communication delay possibly destab...
Iason Vittorias, Julius Kammerl, Sandra Hirche, Ec...