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» A high performance JPEG2000 architecture
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PATMOS
2005
Springer
14 years 3 months ago
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications
In this paper, we present a low power high temperature 80C51 microcontroller. The low power optimizations are applied at gate and architectural level, by using extensive clock and ...
Philippe Manet, David Bol, Renaud Ambroise, Jean-D...
JPDC
2000
141views more  JPDC 2000»
13 years 10 months ago
A System for Evaluating Performance and Cost of SIMD Array Designs
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem ...
Martin C. Herbordt, Jade Cravy, Renoy Sam, Owais K...
ISCAS
2008
IEEE
103views Hardware» more  ISCAS 2008»
14 years 4 months ago
Prediction-based real-time CABAC decoder for high definition H.264/AVC
— This paper proposes a prediction scheme to decode in real-time H.264/AVC bitstream coded in Context-based Adaptive Binary Arithmetic Coding (CABAC). The proposed scheme predict...
WonHee Son, In-Cheol Park
ISCA
2007
IEEE
182views Hardware» more  ISCA 2007»
14 years 4 months ago
Configurable isolation: building high availability systems with commodity multi-core processors
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
Nidhi Aggarwal, Parthasarathy Ranganathan, Norman ...
ISCA
1997
IEEE
113views Hardware» more  ISCA 1997»
14 years 2 months ago
Effects of Communication Latency, Overhead, and Bandwidth in a Cluster Architecture
This work provides a systematic study of the impact of communication performance on parallelapplications in a high performance network of workstations. We develop an experimental ...
Richard P. Martin, Amin Vahdat, David E. Culler, T...