52 search results - page 2 / 11 » A high speed low input current low voltage CMOS current comp... |
ISQED
2003
IEEE
14 years 29 days ago
2003
IEEE
- This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a cha...
MTDT
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby p...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
A high-to-low switching DC-DC converter that operates at input supply voltages up to two times as high as the maximum voltage permitted in a nanometer CMOS technology is proposed ...
GLVLSI
2003
IEEE
14 years 29 days ago
2003
IEEE
A CMOS flash analog-to-digital converter (ADC) designed for high speed and low voltage is presented. Using the Threshold Inverter Quantization (TIQ) comparator technique, a flas...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...