159 search results - page 18 / 32 » A high throughput 3D-bus interconnect for network processors |
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
INFOCOM
2007
IEEE
14 years 2 months ago
2007
IEEE
Next-generation high-end Network Processors (NP) must address demands from both diversified applications and ever-increasing traffic pressure. One major challenge is to design an e...
LCPC
2005
Springer
14 years 1 months ago
2005
Springer
Programming network processors remains a challenging task since their birth until recently when high-level programming environments for them are emerging. By employing domain speci...
IEEEPACT
2007
IEEE
14 years 2 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
ANCS
2009
ACM
13 years 6 months ago
2009
ACM
Ubiquitous multi-core-based web servers and edge routers are increasingly popular in deploying computationally intensive Deep Packet Inspection (DPI) programs. Previous work has s...