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» A high throughput 3D-bus interconnect for network processors
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USENIX
1994
13 years 8 months ago
Reducing File System Latency using a Predictive Approach
Despite impressive advances in file system throughput resulting from technologies such as high-bandwidth networks and disk arrays, file system latency has not improved and in many...
Jim Griffioen, Randy Appleton
RAID
2010
Springer
13 years 5 months ago
GrAVity: A Massively Parallel Antivirus Engine
Abstract. In the ongoing arms race against malware, antivirus software is at the forefront, as one of the most important defense tools in our arsenal. Antivirus software is flexib...
Giorgos Vasiliadis, Sotiris Ioannidis
CASES
2009
ACM
14 years 1 months ago
CGRA express: accelerating execution using dynamic operation fusion
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
Yongjun Park, Hyunchul Park, Scott A. Mahlke
ISPASS
2006
IEEE
14 years 1 months ago
Modeling TCAM power for next generation network devices
Applications in Computer Networks often require high throughput access to large data structures for lookup and classification. Many advanced algorithms exist to speed these searc...
Banit Agrawal, Timothy Sherwood
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 1 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood