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DAC
2006
ACM
14 years 9 months ago
Rapid estimation of control delay from high-level specifications
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda
CADE
2003
Springer
14 years 8 months ago
The Model Evolution Calculus
The DPLL procedure is the basis of some of the most successful propositional satisfiability solvers to date. Although originally devised as a proofprocedure for first-order logic, ...
Peter Baumgartner, Cesare Tinelli
CONCUR
1999
Springer
14 years 21 days ago
Robust Satisfaction
In order to check whether an open system satisfies a desired property, we need to check the behavior of the system with respect to an arbitrary environment. In the most general se...
Orna Kupferman, Moshe Y. Vardi
ECSQARU
2005
Springer
14 years 1 months ago
Conditional Deduction Under Uncertainty
Conditional deduction in binary logic basically consists of deriving new statements from an existing set of statements and conditional rules. Modus Ponens, which is the classical e...
Audun Jøsang, Simon Pope, Milan Daniel
CDES
2007
82views Hardware» more  CDES 2007»
13 years 10 months ago
Efficient Global Fault Collapsing for Combinational Library Modules
—Fault collapsing is the process of reducing the number of faults by using redundance and equivalence/dominance relationships among faults. Exact global fault collapsing can be e...
Hussain Al-Asaad