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ISLPED
2000
ACM
68views Hardware» more  ISLPED 2000»
14 years 7 hour ago
Noise-aware power optimization for on-chip interconnect
Realization of high-performance domino logic depends strongly on energy-efficient and noise-tolerant interconnect design in ultra deep sub-micron processes. We characterize the c...
Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L....
VTS
1996
IEEE
111views Hardware» more  VTS 1996»
13 years 11 months ago
Synthesis-for-scan and scan chain ordering
Designing a testable circuit is often a two step process. First, the circuit is designed to conform to the functional specifications. Then, the testability aspects are added. By t...
Robert B. Norwood, Edward J. McCluskey
FUZZIEEE
2007
IEEE
13 years 11 months ago
An Interval Intelligent-based Approach for Fault Detection and Modelling
Not considered in the analytical model of the plant, uncertainties always dramatically decrease the performance of the fault detection task in the practice. To cope better with thi...
Abbas Khosravi, Joaquim Armengol Llobet, Esteban R...
FATES
2006
Springer
13 years 11 months ago
A Test Calculus Framework Applied to Network Security Policies
Abstract. We propose a syntax-driven test generation technique to auly derive abstract test cases from a set of requirements expressed in a linear temporal logic. Assuming that an ...
Yliès Falcone, Jean-Claude Fernandez, Laure...
ISLPED
1995
ACM
129views Hardware» more  ISLPED 1995»
13 years 11 months ago
CMOS dynamic power estimation based on collapsible current source transistor modeling
When estimating the dynamic power dissipated by a circuit di erent methods ranging from numeric analog simulation to event-driven logic simulation have been proposed. However, as ...
Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Pet...