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» A low complexity hardware architecture for motion estimation
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ISCAS
2008
IEEE
109views Hardware» more  ISCAS 2008»
14 years 2 months ago
A low-area interconnect architecture for chip multiprocessors
— A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost and flexible routing capability. To achieve a low area cost, th...
Zhiyi Yu, Bevan M. Baas
IJES
2007
79views more  IJES 2007»
13 years 7 months ago
Energy-aware compilation and hardware design for VLIW embedded systems
Abstract: Tomorrow’s embedded devices need to run high-resolution multimedia applications which need an enormous computational complexity with a very low energy consumption const...
José L. Ayala, Marisa López-Vallejo,...
ICIP
2007
IEEE
14 years 1 months ago
Rate-Distortion Analysis and Bit Allocation Strategy for Motion Estimation at the Decoder using Maximum Likelihood Technique in
Numerous approaches for distributed video coding have been recently proposed. One of main motivations for these techniques is the possibility of achieving complexity tradeoffs bet...
Ivy H. Tseng, Antonio Ortega
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
14 years 1 months ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha
CASES
2005
ACM
13 years 9 months ago
Hardware support for code integrity in embedded processors
Computer security becomes increasingly important with continual growth of the number of interconnected computing platforms. Moreover, as capabilities of embedded processors increa...
Milena Milenkovic, Aleksandar Milenkovic, Emil Jov...