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» A low complexity hardware architecture for motion estimation
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EGH
2004
Springer
14 years 1 months ago
Mio: fast multipass partitioning via priority-based instruction scheduling
Real-time graphics hardware continues to offer improved resources for programmable vertex and fragment shaders. However, shader programmers continue to write shaders that require ...
Andrew Riffel, Aaron E. Lefohn, Kiril Vidimce, Mar...
ANCS
2009
ACM
13 years 5 months ago
Progressive hashing for packet processing using set associative memory
As the Internet grows, both the number of rules in packet filtering databases and the number of prefixes in IP lookup tables inside the router are growing. The packet processing e...
Michel Hanna, Socrates Demetriades, Sangyeun Cho, ...
AHS
2006
IEEE
164views Hardware» more  AHS 2006»
14 years 1 months ago
Automatic Hybrid Genetic Algorithm Based Printed Circuit Board Inspection
The paper presents a novel integrated system in which a number of image processing algorithm are embedded within a Genetic Algorithm (GA) based framework in order to provide an ad...
Syamsiah Mashohor, Jonathan R. Evans, Ahmet T. Erd...
ISCAS
2006
IEEE
81views Hardware» more  ISCAS 2006»
14 years 1 months ago
Equivalent output-filtering using fast QRD-RLS algorithm for burst-type training applications
— Fast QR decomposition RLS (FQRD-RLS) algorithms are well known for their good numerical properties and low computational complexity. The FQRD-RLS algorithms do not provide acce...
Mobien Shoaib, Stefan Werner, J. A. Apoliná...
VLSID
2005
IEEE
127views VLSI» more  VLSID 2005»
14 years 1 months ago
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model
One of the emerging challenges in formal property verification (FPV) technology is the problem of deciding whether sufficient properties have been written to cover the design in...
Sayantan Das, Ansuman Banerjee, Prasenjit Basu, Pa...