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MICRO
1996
IEEE
129views Hardware» more  MICRO 1996»
14 years 21 days ago
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
Eric Rotenberg, Steve Bennett, James E. Smith
IACR
2011
128views more  IACR 2011»
12 years 8 months ago
Sign Modules in Secure Arithmetic Circuits
In this paper, we study the complexity of secure multiparty computation using only the secure arithmetic black-box of a finite field, counting the cost by the number of secure m...
Ching-Hua Yu
ICIP
2005
IEEE
14 years 10 months ago
Tracking multiple cells by correspondence resolution in a sequential Bayesian framework
We propose a multi-target tracking (MTT) algorithm in a sequential Bayesian framework that computes cell velocities from video microscopy. Unlike the traditional tracking methods,...
Nilanjan Ray, Gang Dong, Scott T. Acton
ISCAS
2006
IEEE
145views Hardware» more  ISCAS 2006»
14 years 2 months ago
The wordlength determination problem of linear time invariant systems with multiple outputs - a geometric programming approach
This paper proposes two new methods for optimizing objectives and constraints. The GP approach is very general and hardware resources in finite wordlength implementation of it allo...
S. C. Chan, K. M. Tsui
DAC
2005
ACM
14 years 9 months ago
Hardware speech recognition for user interfaces in low cost, low power devices
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer