65 search results - page 7 / 13 » A low dynamic power and low leakage power 90-nm CMOS square-... |
IJON
2007
13 years 7 months ago
2007
— This paper, presents a feasability study of a central pattern generator-based analog controller for an autonomous robot. The operation of a neuronal circuit formed of electroni...
PATMOS
2004
Springer
14 years 29 days ago
2004
Springer
Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to tran...
APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— This paper proposes a novel two-phase drive adiabatic dynamic CMOS logic circuit (2PADCL). The proposed 2PADCL uses two complementary sinusoidal power supply clocks and...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
— Long distance, low data-rate UWB communication for sensor network applications requires a highly energy efficient transceiver combined with circuit and system-level optimizati...